1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly relates to a semiconductor device including a plurality of semiconductor chips electrically connected by through silicon vias.
2. Description of Related Art
A memory capacity required in semiconductor memory devices such as DRAM (Dynamic Random Access Memory) is increasing every year. In recent years, there has been proposed a method to meet this requirement. In this method, a plurality of memory chips are stacked and electrically connected via through silicon vias arranged on a silicon substrate (see Japanese Patent Application Laid-open No. 2007-158237).
As an example, a type of semiconductor memory device is considered here, in which an interface chip having front end units such as interface circuits integrated therein and a core chip having back end units such as memory cores integrated therein are stacked. The core chip does not operate as a single chip, because the core chip does not include a front end unit. That is, an interface chip is required to operate a core chip.
Test pads (external terminals) are generally provided in a core chip to make it possible to test an operation of the core chip when it is at a stage of a wafer. A single core chip can be tested without using any interface chip, by sending a test signal to the core chip via test pads.
A signal is sent to a receiver circuit of the core chip from a driver circuit of the interface chip via the through silicon vias. However, the entire chip becomes defective if even one of the through silicon vias is defective, and if a plurality of the chips are stacked, then all the chips become defective. To prevent the entire chip from becoming defective due to a defective through silicon via, auxiliary through silicon vias are sometimes provided in such semiconductor memory devices.
In the semiconductor device disclosed in Japanese Patent Application Laid-open No. 2007-158237, one auxiliary through silicon via is allocated to a group of through silicon vias constituted by a plurality of through silicon vias (for example, eight through silicon vias). If a defect occurs in one of the through silicon vias belonging to the group, the defective through silicon via is relieved by the auxiliary through silicon via allocated to the group.
Because there are auxiliary through silicon vias, one driver circuit selects one through silicon via from the plurality of the through silicon vias. Therefore, a switch (hereinafter, “secondary switch”) becomes necessary at an input side of the receiver circuit to selectively connect to the receiver circuit one path from a plurality of paths that connect each of the through silicon vias to the receiver circuit.
Moreover, a switch (hereinafter, “primary switch”) becomes necessary to selectively connect to the receiver circuit a path between a path that connects a through silicon via to the receiver circuit and a path that connects an external terminal to the receiver circuit.
In the above configuration, when a signal travels from the through silicon via to the receiver circuit, it passes through two switches, namely, the primary switch and the secondary switch.
However, loads of these switches exert a substantial adverse effect on the signal and this may cause degradation in signal quality.
This problem is not limited to semiconductor memory devices such as DRAMs, but can occur to all semiconductor devices including semiconductor chips that are electrically connected to each other via through silicon vias.